NANOARCH 2007 - Call for Papers

CALL FOR PAPERS

Scope -- Author Information -- Committees

Scope

Current defect tolerance, fault-tolerance and manufacturing test techniques are designed under the assumption that a system under test is composed largely of correctly functioning units. However, this assumption is severely tested in emerging nanoelectronics such as molecular electronics, quantum electronics, single electron transistors and carbon nanotubes and nanowires. In these nanoelectronics, self-assembly based fabrication results in failures rates an order of magnitude higher than in traditional CMOS. Consequently, defect and fault tolerance -at the physical, circuit and most importantly at the system level- is an enabling technology for building reliable nanoelectronic systems.

NANOARCH will investigate novel defect and fault tolerance architectures targeting these highly unreliable nanoelectronics. The workshop will be a forum for presenting theoretical, simulation and case studies on new defect models, defect and fault tolerance architectures, associated experimental reliability evaluation and validation frameworks and computer aided simulation and design tools for these emerging nanoelectronics. Topics of interest include but are not limited to:

Defect tolerant nanoelectronic architectures at device, circuit, and system level
Fault tolerant nanoelectronic architectures at the device, circuit, and system level
Emerging computational paradigms for nanoelectronics
Modeling and simulation of novel nanoelectronic architectures and concepts
Implementing micro-architectural concepts using nanoarchitectural building blocks
Dynamic reconfiguration in nanoelectronic architectures
Defect and fault models in emerging nanoelectronic device technologies
Manufacture testing methodologies for nanoelectronic architectures
Yield models, yield analysis and yield enhancement in nanoelectronics
CAD targeting defect and fault-tolerant nanoelectronic architectures

Author Information

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The Program Committee invites authors to submit papers up to 8 pages in length, describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. Electronic submission through the workshop website is required.
The submission of a paper proposal will be considered evidence that upon acceptance, the author(s) will present their paper at the workshop.

The final versions of accepted papers will be included in the NANOARCH Symposium Proceedings

Important Deadlines

Abstracts: March 28, 2007
Full Paper Due: April 4, 2007
Acceptance Notification: May 1, 2007
Final Version of Papers: May 15, 2007

NANOARCH 2007 will have an Official Symposium Proceedings Published by the IEEE.

Committees

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GENERAL CO-CHAIR
Dan Hammerstrom
Prof. of ECE
Portland State University
E-mail: strom@cecs.pdx.edu

GENERAL CO-CHAIR
Ramesh Karri
Assoc. Prof of ECE
Polytechnic University
Tel: 718 260 3596
Cell: 917 363 9703
E-mail: rkarri@poly.edu

PROGRAM CO-CHAIR
Alex Orailoglu
Prof of CSE
University of California, San Diego
Tel: 858 534 0914
E-mail: alex@cs.ucsd.edu

PROGRAM CO-CHAIR
Dr. Clifford Lau
Institute for Defense Analysis
Alexandria, VA
E-mail:clau@ida.org

PUBLICATIONS CHAIR
Garrett Rose
Department of ECE
Polytechnic University
E-mail: grose@duke.poly.edu

For more information, visit us on the web at: http://www.nanoarch.org/

The 3rd IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH’07) is sponsoredby the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).